Phase Lock Basics Egan.pdf
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"In the design of a PLL, the ultimate issue is usually that of minimizing the bandwidth of the tracking system so that a given input step in frequency produces the same fractional change in output frequency. This same bandwidth also sets the maximum PLL frequency response to a given step size in the input signal. The same must be true for PLL system stability. Minimizing PLL bandwidth ensures that the same fractional output change in frequency will produce an identical input change in an anti-phase signal."1
"The goal of the PLL is to maintain a constant phase relationship between a reference signal and a feedback signal. Traditional PLLs are designed to maintain a constant phase relationship and to track a slowly changing frequency. They are not designed to deal with extremely fast changes or to lock extremely high frequency changes. In any case, it would be difficult to track a step change in frequency if the frequency response of the PLL was very high. The high frequency for a TV PLL is in the neighborhood of 5 MHz and the response would need to have a low roll off at that frequency."2
In phase-locked loops (PLLs), even a step in the input signal may cause a step change in the output frequency and a concomitant step change in the output phase. In such cases, the PLL must be designed to increase output frequency by an amount sufficient to bring the feedback signal in phase with the reference signal. The variable counter acts as a phase detector and the PLL is said to be ``frequency tracking.'' On the other hand, in a phase-locked loop (PLL), even a step in the input signal can create a step change in the output frequency. In such cases, the PLL may be said to be ``frequency acquisition». - J. A Neumann, IEEE Transactions on Circuits and Systems, Vol. 15, page 605, 1969
However, the variability inherent in a PLL can be caused by a step in either the input signal or the output frequency frequency. In the first case, the PLL must produce a new output frequency (e.g. d2c66b5586